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1/16 july 2001 n high speed: f max = 53 mhz (typ.) at v cc =6v n low power dissipation: i cc =4 m a(max.) at t a =25 c n high noise immunity: v nih =v nil =28%v cc (min.) n symmetrical output impedance: |i oh |=i ol = 6ma (min) for q a to q d output |i oh |=i ol = 4ma (min) for rco output n balanced propagation delays: t plh @ t phl n wide operating voltage range: v cc (opr) = 2v to 6v n pin and function compatible with 74 series 696 description the m74hc696 is an high speed cmos up / down counter register (3 state) fabricated with silicon gate c 2 mos technology. the m74hc696 is a bcd decade counter with register. the device counts on the positive edge of the counter clock input (cck) when selected by the ocounter modeo. if the input u/d is held oho, the internal counter counts up, and held olo, counts down. the internal counter's outputs are stored in the output register at the positive edge of register clock (rck). the counter features enable p and enable t and a ripple-carry output for easy expansion. the register/counter select input, r/c, selects the counter when low or the register when high for the three state outputs, qa, qb, qc, and qd. both the counter clock ccr and register clock rck are positive-edge triggered. the counter clear cclr is active low and is asynchronous. all inputs are equipped with protection circuits against static discharge and transient excess voltage. m74hc696 pin connection and iec logic symbols order codes package tube t & r dip m74hc696b1r sop m74hc696m1r M74HC696RM13TR tssop m74hc696ttr tssop dip sop u/d decade counter/register (3-state)
m74hc696 2/16 input and output equivalent circuit pin description truth table x : don't care z : high impedance a-d : the level of steady state inputs at inputs a through d respectively. a'-d' : the level of steady state outputs at internal counter outputs qa' through qd' respectively rco = (up qa qd ent + up qa qd ent) pin no symbol name and function 1 u/d up down counter selector 2 cck counter clock 3, 4, 5, 6 a to d data inputs 7, 14 enp/ent enable p and t 8 cclr counter clear (active low) 9 rck register clock 11 r/c counter/register select 12 g enable input 13 load load counter (active low) 15 to 18 qa to qd data outputs 19 rco load counter (active high) 10 gnd ground (0v) 20 v cc positive supply voltage inputs outputs function cclr load enp ent cck u/d rck r/c g qa qb qc qd x x x x x x x x h zzzz high impedance l x x x x x x l l llll c lear counter h l x x x x l l a b c d load counter h h h x x x l l no change no count h h x h x x l l no change no count h h l l h x l l count up count up h h l l l x l l count down count down h x x x x x l l no change no count x x x x x x h l a' b' c' d' load register x x x x x x h l no change no load
m74hc696 3/16 block diagram logic diagram this logic diagram has not be used to estimate propagation delays
m74hc696 4/16 timing chart
m74hc696 5/16 absolute maximum ratings absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied (*) 500mw at 65 c; derate to 300mw by 10mw/ c from 65 cto85 c recommended operating conditions symbol parameter value unit v cc supply voltage -0.5 to +7 v v i dc input voltage -0.5 to v cc + 0.5 v v o dc output voltage -0.5 to v cc + 0.5 v i ik dc input diode current 20 ma i ok dc output diode current 20 ma i o dc output source sink current per output pin (rco) (qa to qd) 25 35 ma i cc or i gnd dc v cc or ground current 70 ma p d power dissipation 500(*) mw t stg storage temperature -65 to +150 c t l lead temperature (10 sec) 300 c symbol parameter value unit v cc supply voltage 2to6 v v i input voltage 0 to v cc v v o output voltage 0 to v cc v t op operating temperature -55 to 125 c t r ,t f input rise and fall time v cc = 2.0v 0 to 1000 ns v cc = 4.5v 0 to 500 ns v cc = 6.0v 0 to 400 ns
m74hc696 6/16 dc specifications symbol parameter test conditio n value unit v cc (v) t a =25 c -40 to 85 c -55 to 125 c min. typ. max. min. max. min. max. v ih high level input voltage 2.0 1.5 1.5 1.5 v 4.5 3.15 3.15 3.15 6.0 4.2 4.2 4.2 v il low level input voltage 2.0 0.5 0.5 0.5 v 4.5 1.35 1.35 1.35 6.0 1.8 1.8 1.8 v oh high level output voltage (qa - qd) 2.0 i o =-20 m a 1.9 2.0 1.9 1.9 v 4.5 i o =-20 m a 4.4 4.5 4.4 4.4 6.0 i o =-20 m a 5.9 6.0 5.9 5.9 4.5 i o =-6.0 ma 4.18 4.31 4.13 4.10 6.0 i o =-7.8 ma 5.68 5.8 5.63 5.60 v oh high level output voltage (rco) 2.0 i o =-20 m a 1.9 2.0 1.9 1.9 v 4.5 i o =-20 m a 4.4 4.5 4.4 4.4 6.0 i o =-20 m a 5.9 6.0 5.9 5.9 4.5 i o =-4.0 ma 4.18 4.31 4.13 4.10 6.0 i o =-5.2 ma 5.68 5.8 5.63 5.60 v ol low level output voltage (qa - qd) 2.0 i o =20 m a 0.0 0.1 0.1 0.1 v 4.5 i o =20 m a 0.0 0.1 0.1 0.1 6.0 i o =20 m a 0.0 0.1 0.1 0.1 4.5 i o =6.0 ma 0.17 0.26 0.33 0.40 6.0 i o =7.8 ma 0.18 0.26 0.33 0.40 v ol low level output voltage (rco) 2.0 i o =20 m a 0.0 0.1 0.1 0.1 v 4.5 i o =20 m a 0.0 0.1 0.1 0.1 6.0 i o =20 m a 0.0 0.1 0.1 0.1 4.5 i o =4.0 ma 0.17 0.26 0.33 0.40 6.0 i o =5.2 ma 0.18 0.26 0.33 0.40 i i input leakage current 6.0 v i =v cc or gnd 0.1 1 1 m a i oz high impedance output leakage current 6.0 v i =v ih or v il v o =v cc or gnd 0.5 5 10 m a i cc quiescent supply current 6.0 v i =v cc or gnd 44080 m a
m74hc696 7/16 ac electrical characteristics (c l = 50 pf, input t r =t f = 6ns) symbol parameter test condition value unit v cc (v) c l (pf) t a =25 c -40 to 85 c -55 to 125 c min. typ. max. min. max. min. max. t tlh t thl output transition time (qn) 2.0 50 25 60 75 90 ns 4.5 7121918 6.0 6101315 t tlh t thl output transition time (rco) 2.0 50 30 75 95 115 ns 4.5 8151923 6.0 7131620 t plh t phl propagation delay time (cck - q) 2.0 50 90 215 270 325 ns 4.5 28 43 54 65 6.0 24 37 46 55 2.0 150 103 245 305 370 4.5 32 49 61 74 6.0 27 42 52 63 t plh t phl propagation delay time (rck - q) 2.0 50 82 185 230 280 ns 4.5 24 37 46 56 6.0 20 31 39 48 2.0 150 95 215 270 325 4.5 28 43 54 65 6.0 24 37 46 55 t plh t phl propagation delay time (cck - rco) 2.0 50 109 245 305 370 ns 4.5 32 49 61 74 6.0 27 42 52 63 t plh t phl propagation delay time (r/c - q) 2.0 50 61 155 195 235 ns 4.5 20 31 39 47 6.0 17 26 33 40 2.0 150 73 185 230 280 4.5 24 37 46 56 6.0 20 31 39 48 t plh t phl propagation delay time (ent - rco) 2.0 50 63 140 175 210 ns 4.5 18 28 35 42 6.0 15 24 30 36 t phl propagation delay time (cclr - q) 2.0 50 78 195 245 295 ns 4.5 26 39 49 59 6.0 22 33 42 50 2.0 150 90 235 295 355 4.5 30 47 59 71 6.0 26 40 50 60 t phl propagation delay time (cclr - rco) 2.0 50 98 220 275 330 ns 4.5 29 44 55 66 6.0 25 37 47 56 f max maximum clock frequency 2.0 50 5 12 4 3.4 mhz 4.5 25 45 20 17 6.0 30 53 24 20
m74hc696 8/16 capacitive characteristics 1) c pd is defined as the value of the ic's internal equivalent capacitance which is calculated from the operating current consumption without load. (refer to test circuit). average operating current can be obtained by the following equation. i cc(opr) =c pd xv cc xf in +i cc /2 (per circuit) t pzl t pzh high impedance output enable time 2.0 50 r l =1k w 45 120 150 180 ns 4.5 15 24 30 36 6.0 13 20 26 31 2.0 150 r l =1k w 57 150 190 225 ns 4.5 19 30 38 45 6.0 16 26 32 38 t plz t phz high impedance output disable time 2.0 50 r l =1k w 32 115 145 175 ns 4.5 17 23 29 35 6.0 14 20 25 30 t w(l) t w(h) minimum pulse width (cck, rck) 2.0 50 40 75 95 110 ns 4.5 8151922 6.0 7131619 t w(l) minimum pulse width (cclr) 2.0 50 40 75 95 110 ns 4.5 8151922 6.0 7131619 t s minimum set-up time (load, ent, enp) 2.0 50 64 150 190 220 ns 4.5 16 30 38 44 6.0 14 26 32 37 t s minimum set-up time (a, b, c, d) 2.0 50 16 50 65 75 ns 4.5 4101315 6.0 3 9 11 13 t s minimum set-up time (cck - rck) 2.0 50 44 100 125 150 ns 4.5 11 20 25 30 6.0 9172126 t s minimum set-up time (u/d) 2.0 50 44 100 125 145 ns 4.5 11 20 25 29 6.0 9172125 t h minimum hold time 2.0 50 555 ns 4.5 5 5 5 6.0 5 5 5 t rem minimum removal time 2.0 50 555 ns 4.5 5 5 5 6.0 5 5 5 symbol parameter test condition value unit v cc (v) t a =25 c -40 to 85 c -55 to 125 c min. typ. max. min. max. min. max. c in input capacitance 5101010pf c pd power dissipation capacitance (note 1) 71 pf symbol parameter test condition value unit v cc (v) c l (pf) t a =25 c -40 to 85 c -55 to 125 c min. typ. max. min. max. min. max.
m74hc696 9/16 test circuit c l = 50pf/150pf or equivalent (includes jig and probe capacitance) r 1 =1k w or equivalent r t =z out of pulse generator (typically 50 w ) waveform 1 : minimum pulse width, propagation delay time (f=1mhz; 50% duty cycle) test switch t plh ,t phl open t pzl ,t plz v cc t pzh ,t phz gnd
m74hc696 10/16 waveform 2 : minimum pulse width, removal time (f=1mhz; 50% duty cycle) waveform 3 : minimum setup and hold time (f=1mhz; 50% duty cycle)
m74hc696 11/16 waveform 4 : minimum setup and hold time, pulse width, propagation delay time (f=1mhz; 50% duty cycle) waveform 5 : propagation delay time (f=1mhz; 50% duty cycle)
m74hc696 12/16 waveform 6 : minimum setup and hold time (f=1mhz; 50% duty cycle) waveform 7 : output enable and disable time (f=1mhz; 50% duty cycle) waveform 8 : minimum setup and hold time (f=1mhz; 50% duty cycle)
m74hc696 13/16 dim. mm. inch min. typ max. min. typ. max. a1 0.254 0.010 b 1.39 1.65 0.055 0.065 b 0.45 0.018 b1 0.25 0.010 d 25.4 1.000 e 8.5 0.335 e 2.54 0.100 e3 22.86 0.900 f 7.1 0.280 i 3.93 0.155 l 3.3 0.130 z 1.34 0.053 plastic dip-20 (0.25) mechanical data p001j
m74hc696 14/16 dim. mm. inch min. typ max. min. typ. max. a 2.65 0.104 a1 0.1 0.2 0.004 0.008 a2 2.45 0.096 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.012 c 0.5 0.020 c1 45 (typ.) d 12.60 13.00 0.496 0.512 e 10.00 10.65 0.393 0.419 e 1.27 0.050 e3 11.43 0.450 f 7.40 7.60 0.291 0.300 l 0.50 1.27 0.020 0.050 m 0.75 0.029 s8 (max.) so-20 mechanical data po13l
m74hc696 15/16 dim. mm. inch min. typ max. min. typ. max. a 1.2 0.047 a1 0.05 0.15 0.002 0.004 0.006 a2 0.8 1 1.05 0.031 0.039 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0089 d 6.4 6.5 6.6 0.252 0.256 0.260 e 6.2 6.4 6.6 0.244 0.252 0.260 e1 4.3 4.4 4.48 0.169 0.173 0.176 e 0.65 bsc 0.0256 bsc k0 8 0 8 l 0.45 0.60 0.75 0.018 0.024 0.030 tssop20 mechanical data c e b a2 a e1 d 1 pin 1 identification a1 l k e 0087225c
m74hc696 16/16 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringe ment of patents or other righ ts of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this pub lication are subject to change without notice. thi s pub lication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authori zed for use as critical components in life suppo rt devices or systems without express written approval of stmicroelectronics. ? the st logo is a registered trademark of stmicroelectronics ? 2000 stmicroelectronics - printed in italy - all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco singapore - spain - sweden - swit zerland - united kingdom ? http://w ww.st.com

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